Staff Digital IC Design Engineer

Qualifications

• Hands on experience with RTL design using Verilog and/or System Verilog
• Hands on experience with Lint, CDC, code coverage
• Understanding on verification and test cases development
• Experience in some of the SOC architectures: top level, IP integration, CPUs, external interfaces (PCIe, serial, DDR/Flash), internal busses, NOCs, peripherals, clock/reset architectures
• System knowledge in communications domain and its interface protocols is a plus
• Experience in DSP design
• Knowledge of ing and programming using Perl, Python, tcl, for automation is a plus
• Experience with designing for low power, including power simulation and analysis
• Experience with high-speed digital design interfacing to Mixed Signal IP is a plus
• Experience in FPGA design or emulation
• Prototype lab bring-up and silicon validation experience would be an asset
• Strong logical and creative problem-solving skills with excellent analytical and debugging skills
• Excellent written and good verbal English communication skills and teamwork
• Experience to work with cross functional and multi-site teams

Responsibilities:

• Support ASIC SOC/IP design and development at various stages including from initial feasibility through to final device production
• Creation of SOC/IP block level and/or device level RTL for efficient power / area / performance design and implementation
• Work closely with mixed signal teams for integration of high-speed analog circuits
• Work closely with the verification team on test plan and debug/fix failing test cases